AMS Verification (Analog Mixed Signal Verification) Resume

Candidate Pitch:

Role: AMS Verification (Analog Mixed Signal Verification) Location: HYBRID - Mountain View CA , Austin TX, Portland OR, Fort Collins CO Job Type: FTE/Permanent Interview: Phone/Skype Keywords will be Analog Mixed signal DV, Mixed-signal RTL Experience wise ~5 years to 10 years Tasks preferably - SERDES verification, ADC / DAC verification, … I am ok with AMS RTL folks too but they have should have AMS heavy experience Responsibilities: Responsible for performing verification for AMS designs. Create UVM benches for mixed signal blocks and developing test scenarios. Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage Write assertions and checkers for the properties and corner cases Analyze verification coverage and improve the test cases Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation Requirements: ● Detailed knowledge of verification using SystemVerilog ● Experience with creating UVM based testbenches for Analog Mixed-Signal applications ● Experience with assertion based verification for analog blocks ● Experience with power aware verification with UPF will be a plus ● UVM-AMS experience preferred ● Experience with sv-real preferred ● Scripting skills in perl / python is preferred ● Excellent communication skills ● Team player with an ability to encourage team members Education & Experience: ● MS (preferred in EE and CE) plus 5 years Role: AMS Verification (Analog Mixed Signal Verification) Location: HYBRID - Mountain View CA , Austin TX, Portland OR, Fort Collins CO Job Type: FTE/Permanent Interview: Phone/Skype Keywords will be Analog Mixed signal DV, Mixed-signal RTL Experience wise ~5 years to 10 years Tasks preferably - SERDES verification, ADC / DAC verification, … I am ok with AMS RTL folks too but they have should have AMS heavy experience Responsibilities: Responsible for performing verification for AMS designs. Create UVM benches for mixed signal blocks and developing test scenarios. Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage Write assertions and checkers for the properties and corner cases Analyze verification coverage and improve the test cases Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation Requirements: ● Detailed knowledge of verification using SystemVerilog ● Experience with creating UVM based testbenches for Analog Mixed-Signal applications ● Experience with assertion based verification for analog blocks ● Experience with power aware verification with UPF will be a plus ● UVM-AMS experience preferred ● Experience with sv-real preferred ● Scripting skills in perl / python is preferred ● Excellent communication skills ● Team player with an ability to encourage team members Education & Experience: ● MS (preferred in EE and CE) plus 5 years Education & Experience: ● MS (preferred in EE and CE) plus 5 years Role: AMS Verification (Analog Mixed Signal Verification) Location: HYBRID - Mountain View CA , Austin TX, Portland OR, Fort Collins CO Job Type: FTE/Permanent Interview: Phone/Skype Keywords will be Analog Mixed signal DV, Mixed-signal RTL Experience wise ~5 years to 10 years Tasks preferably - SERDES verification, ADC / DAC verification, … I am ok with AMS RTL folks too but they have should have AMS heavy experience Responsibilities: Responsible for performing verification for AMS designs. Create UVM benches for mixed signal blocks and developing test scenarios. Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage Write assertions and checkers for the properties and corner cases Analyze verification coverage and improve the test cases Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation Requirements: ● Detailed knowledge of verification using SystemVerilog ● Experience with creating UVM based testbenches for Analog Mixed-Signal applications ● Experience with assertion based verification for analog blocks ● Experience with power aware verification with UPF will be a plus ● UVM-AMS experience preferred ● Experience with sv-real preferred ● Scripting skills in perl / python is preferred ● Excellent communication skills ● Team player with an ability to encourage team members Education & Experience: ● MS (preferred in EE and CE) plus 5 years Role: AMS Verification (Analog Mixed Signal Verification) Location: HYBRID - Mountain View CA , Austin TX, Portland OR, Fort Collins CO Job Type: FTE/Permanent Interview: Phone/Skype Keywords will be Analog Mixed signal DV, Mixed-signal RTL Experience wise ~5 years to 10 years Tasks preferably - SERDES verification, ADC / DAC verification, … I am ok with AMS RTL folks too but they have should have AMS heavy experience Responsibilities: Responsible for performing verification for AMS designs. Create UVM benches for mixed signal blocks and developing test scenarios. Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage Write assertions and checkers for the properties and corner cases Analyze verification coverage and improve the test cases Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation Requirements: ● Detailed knowledge of verification using SystemVerilog ● Experience with creating UVM based testbenches for Analog Mixed-Signal applications ● Experience with assertion based verification for analog blocks ● Experience with power aware verification with UPF will be a plus ● UVM-AMS experience preferred ● Experience with sv-real preferred ● Scripting skills in perl / python is preferred ● Excellent communication skills ● Team player with an ability to encourage team members Education & Experience: ● MS (preferred in EE and CE) plus 5 years Role: AMS Verification (Analog Mixed Signal Verification) Location: HYBRID - Mountain View CA , Austin TX, Portland OR, Fort Collins CO Job Type: FTE/Permanent Interview: Phone/Skype Keywords will be Analog Mixed signal DV, Mixed-signal RTL Experience wise ~5 years to 10 years Tasks preferably - SERDES verification, ADC / DAC verification, … I am ok with AMS RTL folks too but they have should have AMS heavy experience Responsibilities: Responsible for performing verification for AMS designs. Create UVM benches for mixed signal blocks and developing test scenarios. Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage Write assertions and checkers for the properties and corner cases Analyze verification coverage and improve the test cases Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation Requirements: ● Detailed knowledge of verification using SystemVerilog ● Experience with creating UVM based testbenches for Analog Mixed-Signal applications ● Experience with assertion based verification for analog blocks ● Experience with power aware verification with UPF will be a plus ● UVM-AMS experience preferred ● Experience with sv-real preferred ● Scripting skills in perl / python is preferred ● Excellent communication skills ● Team player with an ability to encourage team members Education & Experience: ● MS (preferred in EE and CE) plus 5 years Role: AMS Verification (Analog Mixed Signal Verification) Location: HYBRID - Mountain View CA , Austin TX, Portland OR, Fort Collins CO Job Type: FTE/Permanent Interview: Phone/Skype Keywords will be Analog Mixed signal DV, Mixed-signal RTL Experience wise ~5 years to 10 years Tasks preferably - SERDES verification, ADC / DAC verification, … I am ok with AMS RTL folks too but they have should have AMS heavy experience Responsibilities: Responsible for performing verification for AMS designs. Create UVM benches for mixed signal blocks and developing test scenarios. Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage Write assertions and checkers for the properties and corner cases Analyze verification coverage and improve the test cases Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation Requirements: ● Detailed knowledge of verification using SystemVerilog ● Experience with creating UVM based testbenches for Analog Mixed-Signal applications ● Experience with assertion based verification for analog blocks ● Experience with power aware verification with UPF will be a plus ● UVM-AMS experience preferred ● Experience with sv-real preferred ● Scripting skills in perl / python is preferred ● Excellent communication skills ● Team player with an ability to encourage team members Education & Experience: ● MS (preferred in EE and CE) plus 5 years