SOC Design Verification Engineer Job

ALTERA CORPORATION
Verification lead for Full Chip, Multi-die chiplets and subsystems. Developing test plans, BFM integration, and verification environment bring-up. Test plan execution involving reset, boot sequence, PLA generation, integration & validation, and low power verification of multi-die SoCs. Performing GLS and PLA verification at SoC level zero delay/unit delay, and SDF timing simulations in Intel’s 14nm, 10nm, 7nm, 4nm, 3nm, and 18A technologies. Collaborating with cross-functional teams including architecture, design, physical/structural design, DFT, clocking, timing, and post-silicon teams. Supporting DFT and ATPG teams on GLS model build. Contributing to TR, architecture discussions, verification planning, and execution timeline discussions. Supporting post-silicon debug issues. Debug and fix bugs for failed tests. Telecommuting may be permitted. When not telecommuting, must report to worksite. Bachelor’s degree in Electrical/Electronics Engineering, Computer Engineering, or related and 5 years of experience OR Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or related and 3 years of experience. To apply email resume to [email protected] and reference job #9391243