SoC Design Verification Engineer Job
If this is a scam...
Mark as SPAM
Thank you for helping!...
Undo
Employer: Chelsea Goff
SpiderID: 14191561
Location: Austin, Texas
Posted: 6/8/2026
Wage: $110,656 - $146,000
Priority Review Date: 7/8/2026
Job Code / NOC / SOC: 9391228
Category: General
Job Description:
ALTERA CORPORATION
• Working closely with architecture and RTL designers on verifying the functionality correctness of the design.
• Generating directed and constrained random tests, analyze coverage models, and enhance testbenches to increase coverage.
• Additionally, building automated flows for block and chip-level verification, debug failures, manage bug tracking, and ensure coverage closure.
• Creating verification plan from specification and in coordination with architects.
• Building automated flows using scripting language, such as Perl or Python, for block and chip level verification.
• Debugging failures, running simulations, manage bug tracking, and close coverage.
• Developing tests in SystemVerilog, and advanced verification methodologies, including UVM, formal verification, and assertion-based verification to test plans.
• Developing checkers in SystemVerilog or UVM environment to verify the design
Telecommuting may be permitted. When not telecommuting, must report to worksite. Master’s degree in Electrical Engineering, Computer Engineering, or related and 1 year of experience. Salary Range: $110,656 - $146,000. To apply email resume to [email protected] and reference job#9391228
• Working closely with architecture and RTL designers on verifying the functionality correctness of the design.
• Generating directed and constrained random tests, analyze coverage models, and enhance testbenches to increase coverage.
• Additionally, building automated flows for block and chip-level verification, debug failures, manage bug tracking, and ensure coverage closure.
• Creating verification plan from specification and in coordination with architects.
• Building automated flows using scripting language, such as Perl or Python, for block and chip level verification.
• Debugging failures, running simulations, manage bug tracking, and close coverage.
• Developing tests in SystemVerilog, and advanced verification methodologies, including UVM, formal verification, and assertion-based verification to test plans.
• Developing checkers in SystemVerilog or UVM environment to verify the design
Telecommuting may be permitted. When not telecommuting, must report to worksite. Master’s degree in Electrical Engineering, Computer Engineering, or related and 1 year of experience. Salary Range: $110,656 - $146,000. To apply email resume to [email protected] and reference job#9391228
Contact Information:
| Contact Name: Chelsea Goff | Type: Employer |
| Company: ALTERA CORPORATION |