Senior FPGA Design Verification Engineer Job

Title: Senior FPGA Design Verification Engineer
Location: Dedham, MA
Job Type: Full-Time/Permanent
Sign-on Bonus: Up to $3000 for New Hires

Summary:
As a Senior FPGA Design Verification Engineer, you will be a key member of a cross-functional team, responsible for the design of secure, cost-sensitive products from system architecture and requirements allocation through to product release and production.

Basic Qualifications:
Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering, or Mathematics field, with at least 8 years of relevant experience; or Master's degree with at least 6 years of relevant experience.

Preferred Skills or Experiences:
Experience with OVM/UVM design verification methodology
Proficiency in scripting languages such as bash/csh, Perl, TCL, Python, or similar
Familiarity with VHDL or similar hardware description languages.

What Sets You Apart:
Experience defining verification methodology for complex FPGAs
Ability to analyze requirements, create test plans, and build scalable simulation environments using SystemVerilog/UVM
Familiarity with testing complex designs, including code coverage, functional coverage, and assertions
Experience in dynamic environments with changing needs and requirements
FPGA/ASIC design experience is a plus
Familiarity with FPGA & advanced verification tools is a plus
Strong team player who thrives in collaborative environments and celebrates team success.

Our Commitment to You:
Exciting career path with continuous learning and development opportunities
Research-driven work with teams focused on practical solutions
Flexible schedules, including the option for every other Friday off (9/80 schedule)

Health/Dental Benefits, Retirement Benefits, Paid Holidays, Vacations, and Sick Leave, Life and/or Disability Insurance, Relocation Assistance, Other Benefits