Design Verification Engineer Job

Requisition Title: Design Verification Engineer
Location: San Jose, CA / San Diego, CA / Austin, TX (Hybrid)
Duration: 6 months contract
Job Description:
As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.

Requirements:
• 5-15 year’s industry experience in a design verification role.
• Proficient in System Verilog/UVM/OVM, OOP/C
• Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
• Experience with code coverage and functional coverage driven verification methodology.
• Experience in creating, running and debugging of System Verilog/UVM constraint-random Testbench.
• Excellent working knowledge of scripting languages such as Python or Perl.
• Understanding of micro-architecture, logic design, FSMs, arithmetic Datapath pipelines.
• Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
• Strong debugging skills
• Strong programming skills with good understanding of algorithms and data structures
• Good verbal and written communication skills

Thanks,
Email: [email protected]

Requirements:
• 5-15 year’s industry experience in a design verification role.
• Proficient in System Verilog/UVM/OVM, OOP/C
• Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
• Experience with code coverage and functional coverage driven verification methodology.
• Experience in creating, running and debugging of System Verilog/UVM constraint-random Testbench.
• Excellent working knowledge of scripting languages such as Python or Perl.
• Understanding of micro-architecture, logic design, FSMs, arithmetic Datapath pipelines.
• Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage