IC design engineer - Electrician Resume Search
IC design engineer - Electrician Resume Search
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IC design engineer Resume

Desired Industry: Electrician SpiderID: 41329
Desired Job Location: Boston, Massachusetts Date Posted: 8/8/2010
Type of Position: Contractor Availability Date:
Desired Wage:
U.S. Work Authorization:
Job Level: Experienced with over 2 years experience Willing to Travel:
Highest Degree Attained: Willing to Relocate:

Mixed signal ASIC design, communication systems, DSP.

- 20 years ASIC digital and mixed signal IC’s
- 6 years Communication/DSP
- 8 years RF and Analog mixed signal IC’s

1977-1983 Moscow Institute of Physics and Technology.
Qualification: Master of science Engineer-physicist, IC design.

Schematic design/simulation/layout RF, Analog and Digital components, transistor level design, project verification (DRC/ERC/LVS, parasitic extraction).
Synthesis(Verilog/VHDL), RTL-design, digital cells routing, IO-cells design, FPGA design.
Experienced with PC and SUN station: “Mentor Graphics” (“Calibre”, “Eldo” “HDL Designer”, “ModelSim”, “Leonardo”), “CADENCE”(Analog artist/Virtuoso), “Hspice”, “Tanner EDA”, Matlab/Simulink, C, Tcl.

Additional Information:
“Panavision Imaging, LCC” (Homer, NY, USA).
2010 - Imaging IC design, IC Design Engineer.

Design of the imaging sensor IC for video application - 6xHDTV resolution, 12-17 Mpix, 48-120 fps (A/D 10-12 bit, Dynamic Range ~70dB, 4-8 el. rms noise, clock ~200 MHz, Power ~4 W).

“Custom One Design Inc.” (Melrose, MA, USA).
1999-2009 – RF and Analog mixed signal IC design (0.18 um CMOS), Senior RF Design Engineer.

Chip designs

- RF-Transceiver and GPS-receiver - design Sigma-Delta PLL, digital multi-bit Sigma-Delta modulator (Simulink and Verilog models), reduction of quantization noise, PLL components, DSP-circuits.
- Design of the Sigma-Delta ADC for CAT-scanners – the most precision solution for image sensors array readout – Simulink model, high-precision SC-circuits design, suppression noises (kT/C, 1/f, OpAmp noise), FIR, transistor level design, Spice simulation.
- Mixed signal chip for Blood sugar meter for “NOVA”, design works on first silicon. Design includes DC-DC convertor, power transistors, A/D convertor, OpAmps, digital part.

Single chip CMOS Direct Conversion Tranceiver (1.4 GHz RF-components), single chip low-IF CMOS GPS-receiver (3.5 GHz RF-components).
Sigma-Delta Frequency Synthesizer, PLL, Subharmonic Mixer, Phase shifter, Prescaler. Special high symmetrical RF-Mixer layout for harmonics and noise suppression – results on silicon was better than simulation. Symmetrical baseband layout to minimize I/Q-distortions. Component isolation (digital, analog, RF). CML-logic for RF-applications - frequency division 5 times faster than CMOS, low-noise. Special low noise Digital Library and Pads for mixed signal application.

Software Defined Radio (SDR) - subsampling BP-Sigma-Delta receiver, totally digital control currier frequency and bandwidth, DSP.

SC-circuits design – suppression 1/f and kT/C noises, chopping, auto-zero and correlated double sampling technics, suppress influence of finite Gain of the OpAmps. Active filters design.

Multi-phase oscilator and phase grid generator for UWB-radars and Radio Imaging – 256 phases, step 20ps, jitter<3.5ps

Layout design:
1. I/O cells layout - I/O cell library, LVDS-pads, ESD-protection, RF-ESD, Pad Ring design. Layout provide uniform current distribution to avoid overload ESD-protection.
2. Digital layout – Standard Cell Library, Place and Route, clock tree generation, high frequency layout, fast CML cells for RF applications - frequency division 5 times faster than CMOS.
3. Array layout - RAM/ROM/Image sensors array layout

4. RF/Analog layout
Automatic generation of the component’s layout (Mentor IC station, Tanner EDA)
- RF /Analog transistors (including guard rings)
- MIM-Cap
- Inductance
manual routing of the RF/analog components. This approach allows to get good correspondence between component’s layout and spice models, results are relatively independent on layout person.

Special technic to improve device matching for analog components (centroid).
Special high symmetrical RF-layout for harmonics and noise suppression.
RF-layout – LNA, VCO, Mixer, AGC, PA, PLL, CML-prescaler and Phase shifter, RF-IOs.
High frequency layout, minimization of parasitics, shielded buses, I/O cells with low EMI radiation.
Symmetrical baseband layout to minimize I/Q-distortions.
Component isolation (digital, analog, RF). Triple well isolation. Substrate noise reduction. Low noise digital library and I/O cells.
High voltage layout (LDMOS, component isolation, latch-up prevention), radiation hardened layout.
Top level floor-plan and routing, power/GND buses distributions, clock buses distribution.
Layout of wires to meet RC and characteristic impedance requirements, critical path routing.
Calculation of power supply bus IR drop and electro-migration analysis.
Project verification (DRC/ERC/LVS, parasitic extraction).

Experience with Sigma-Delta.
Solve the problem of stability for the Sigma-Delta-modulators of arbitrary order (not MASH-structure). This problem is not scientifically solved yet. Check with Simulink model the stability of the Sigma-Delta-modulators up to 9-order. This allows to get some important practical results
- High-precision high-order Sigma-Delta ADC not sensitive to component mismatch, unlike MASH-structure - no calibration is necessary. Good for mass production.
- High-order continuous time Sigma-Delta ADC, no antialiasing filter, no kT/C noise. Proposed structure doesn’t sensitive to the main drawbacks of the continuous time Sigma-Delta Modulator - poor matching and RC temperature dependency.
- Multi-bit digital Sigma-Delta Modulator with decreased quantization noise, for particular input value low output voltage swing – two nearest levels in multi-level quantizer. New approach - good for Sigma-Delta PLL and DACs.
- Multi-bit digital Sigma-Delta Modulator with decreased quantization noise, Sigma-Delta Modulator has minimum possible output voltage swing – two nearest levels in multi-level quantizer. New approach - good for Sigma-Delta PLL and DACs.

Design of the Incremental Sigma-Delta ADC (new type of ADC actively developing since 2005) - 10 times faster thermal noise suppression than standard architecture, few times faster quantization noise suppression, much simpler structure – good for multichannels solutions (a few hundreds channels on chip).

Sigma-Delta ADC with current sensitive input, removing Current-to-Voltage conversion limiting the performance. Maximum precision for Current-to-Voltage conversion ~16-17 bit, Sigma-Delta ADC ~20-24 bit. This approach allows get theoretical limit precision for image sensors.

Sigma-Delta ADC for varible input signal, output is equal to integral of input value. Combining Sigma-Delta processig with input signal integration allows substantionally improve performance (new approach, a lot of applications).

Band-Pass Sigma-Delta ADC – programmable Band-Pass filter, combinig Sigma-Delta processig with DSP allows to perform DSP without multiplications, easy to make compact high-order filters.

Experience with transistor level design – Schematic/Layout, Spice simulation.
Experience with high-level design – Verilog, Matlab/Simulink, C, Tcl.

“MIEE”(Zelenograd, Moscow, Russia)/”Ericsson” (Stockholm, Sweden)
1994-1999 – Spread spectrum communication systems (CDMA) – DSP - Hilbert transform, cos/sin-filters, Complex Multiplication, FIR – Band Pass/Low Pass, PLL, direct frequency synthesis, acquisition and tracking units, digital Intermediate Frequency (IF) unit, Subsampling receiver, capability to work in high-noise environment.

”Nauchny Center” (Zelenograd, Moscow, Russia)
1993-1994 – Optoelectronic CMOS IC for adaptive optics and for satellites observation systems. Image sensors array design.

“MIEE”/”Nauchny Center” (Zelenograd, Moscow, Russia)
1990-1993 – Design data-processor for Massively Parallel Processor architecture of SIMD type (similar to Connection Machine). Design functional circuit of 32-bit RISC-processor. Design VLIW-architecture for digital signal processing. Design of the different processor’s units - FastAdder/Multiplier/RegisterFile.

“Exiton” (Pavlovsky-Posad, Moscow region, Russia).
1988-1990 – Radiation hardened CMOS ASIC design, high-voltage CMOS design.

“Moscow Institute of Physics and Technology” (Moscow, Russia).
1984-1988 - High-speed bipolar IC design for vector supercomputer (similar to Cray).

2010 – “Panavision Imaging, LCC” (Homer, NY, USA). IC Design Engineer, Imaging IC design.
1999-2009 – “Custom One Design, Inc.” (Melrose, MA, USA). Senior RF Design Engineer, RF and Analog mixed signal IC design.
1994-1999 – “MIEE”(Zelenograd, Moscow, Russia)/”Ericsson” (Stockholm, Sweden). Chief of group, spread spectrum communication systems design.
1993-1994 – ”Nauchny Center” (Zelenograd, Moscow, Russia). Leading engineer, ASIC design.
1990-1993 – “MIEE”/”Nauchny Center” (Zelenograd, Moscow, Russia). Leading engineer, microprocessor design.
1988-1990 – “Exiton” (Pavlovsky-Posad, Moscow region, Russia). CMOS ASIC designer.
1984-1988 - Moscow Institute of Physics and Technology (Moscow, Russia). High-speed bipolar IC designer.

Available upon request.

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