Process Integration Engineer-Semiconductors - Engineering Resume Searc
Process Integration Engineer-Semiconductors - Engineering Resume Searc
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Process Integration Engineer-Semiconductors Resume


Desired Industry: Engineering SpiderID: 53161
Desired Job Location: Haymarket, Virginia Date Posted: 8/1/2011
Type of Position: Full-Time Permanent Availability Date: Immediately
Desired Wage: 80000
U.S. Work Authorization: Yes
Job Level: Experienced with over 2 years experience Willing to Travel: Yes, 25-50%
Highest Degree Attained: Bachelors Willing to Relocate: No


Objective:
Highly capable, dynamic, and seasoned
professional with more than 10 years of
engineering experience in semiconductor
industries. Demonstrates adeptness in
management and data analysis, capable of
executing leadership and rendering
direction to other engineers and
technicians as well as analyzing data
using different methods.
Results-driven professional, with proven
track record of finishing projects on
time, with high quality and no errors.
Effective team player, relied upon to
resolve problems others could not handle
and complete urgent tasks.
Equipped with excellent interpersonal
and communication skills, able to
effectively deal with individuals from
all levels to resolve conflicts. Fluent
in Serbo-Croatian, German and English.


Experience:
MICRON TECHNOLOGY
Manassas, VA, USA 2008–Present
Boise, ID, USA 1998–2008

Module Support Engineer, Fab 6 (MTV)
2008–Present

Spearhead the planning and
implementation of process changes in the
capacitor module in DRAM; perform
process characterization by using SWRs
and conversion methods; and implement
new process changes by conducting
analysis of special work requests (SWR)
and conversion data (probe and Param).

- Continuously improve processes,
implement changes, and communicate
process changes to the worldwide
community in order to achieve benchmark
objectives, including utilizing
statistical process control (SPC)
methods to maintain and enhance inline
metrics.
- Ensure defect reduction by
working with process areas and inline
defects detection groups as well as
improve defect density by collaborating
with PYE to enable backend yield and
server eligibility.
- Maximize fab output and reduce
cost through process qualification and
process changes.

Junior Engineer-Process Lead, Fab 1 Real
Time Defect Analysis (RDA) 2008

Performed monitoring and investigation
of SPC charts for shifts, trends, and
other variations that could be related
to process or equipment issues.
Conducted follow-up on recent excursion;
assisted excursion engineer in preparing
reports and identified all affected
lots.

- Achieved yield improvement and
defect reduction through extensive data
analysis and data extraction tools such
as JMP, IDAS and Yield3.
- Resolved possible yield hit
lots, problem lots, and other major
issues that fab process engineers were
not able to address
- Identified new defects and
reduced inline defects in collaboration
with process engineers, equipment
engineers, and process module owners.

Junior Engineer-Lead Engineer, Fab 1
Real Time Defect Analysis (RDA)
2006–2008

Supervised process engineers, process
technicians, equipment technicians, and
SEM technicians; ensured their safety;
conducted performance evaluations; and
provided direction and feedback on their
professional development.
Served as the main contact person in
production as well as various fab-
related issues to other process
engineers and rendered participation in
inter-departmental processes as well as
equipment development projects.

- Effectively managed product
across multiple tools utilizing
inspection equipment, maintaining tools
and reducing inline defects by working
closely with process lead engineers and
production supervisors.
- Provided instruction on the Data
Tracking System (DTS) class to Chemical-
Mechanical Planarization (CMP), Wet
Process and Metals engineers. Taught
Klarity class to CMP engineers.

Junior Engineer-Process Engineer, Fab 1
Real Time Defect Analysis (RDA)
2002–2006

Handled the DTS notification and
documentation for major issues and
potential massive yield hits. Directly
trained and facilitated training to new
shift personnel.

- Analyzed defects and determined
root causes by using scanning electron
microscopy (SEM) and accurately
identified offending equipment to
prevent downtime utilizing extensive
troubleshooting skills, process
knowledge, and interaction with
engineers from other manufacturing
areas.
- Ensured that major excursions
and yield losses were prevented by
monitoring SPC charts, analyzing trends
and variations for specific tools and/or
process issues.
- Determined the root cause of
defects to improve yields by analyzing
the chemical composition of defects
using Energy Dispersive Spectroscopy
(EDS).

Junior Engineer-Process Engineer, Fab 1
Param Group 1998–2002
Served as the Fab 1 Param engineer for
Back End of the Line (BEOL) for all part
types, handling the ramping of 61 ILD
polish step on DRAM and providing SPC
data support. Supplied trending and web
reporting probe yields and inline data;
performed tool and recipe conversions;
and worked on better utilization of fab
equipment.

- Reduced defects at the Metal 1
and Metal 2 levels; worked on process
conversion for NAND, DRAM, SRAM and CMOS
part types; and instrumental in the
replacement of 60 Etch process on DRAM.
- Performed data extraction and
tools analysis (JMP, IDAS, and Yield3)
to handle projects for yield
improvements and defect reduction.


EARLIER CAREER

HAUSPFLEGE STATION REUTLINGEN ~
Reutlingen, Germany
Social Worker 1995–1997

- Provided counseling to families
on social and economic issues.

HIGH SCHOOL JAROSLAV CERNI ~ Sarajevo,
Yugoslavia
High School Math and Electronics Teacher
1992–1994

- Prepared students for
International math and electronic
competitions and led efforts in the
establishment and maintenance of a
technical laboratory.

TEO UNIONINVEST ~ Sarajevo, Yugoslavia
Design Engineer for Electrical Equipment
1991–1992

- Determined reliable and
appropriate materials to the design and
prepared engineering estimates for
custom-designed electrical supply
stations.


Education:
Bachelor of Science in Electrical
Engineering ~ University of Sarajevo ~
Sarajevo, Yugoslavia
MICRON LEADERSHIP PROGRAM: 2011


Affiliations:
---------


Skills:
LEADERSHIP/SUPERVISION
TRAINING/TEACHING
DEFECTS IDENTIFICATION
ROOT CAUSE ANALYSIS
YIELD IMPROVEMENT
DEFECT REDUCTION
PROCESS IMPROVEMENT AND CHANGES
STATISTICAL PROCESS CONTROLS (SPC)
METHODS


Additional Information:
Technical Acumen

NANOMETER SCALE CLEANROOM PROCESSING ~
SCANNING ELECTRON MICROSCOPY (SEM) ~
ENERGY DISPERSIVE SPECTROSCOPY (EDS) ~
JMP ~ MICROSOFT EXCEL, WORD, POWERPOINT,
AND MICROSOFT OUTLOOK


Reference:
Available upon request.


Candidate Contact Information:
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