VLSI Engineer - Engineering Resume Search
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VLSI Engineer Resume


Desired Industry: Engineering SpiderID: 36620
Desired Job Location: San Jose, California Date Posted: 5/1/2010
Type of Position: Full-Time Permanent Availability Date:
Desired Wage:
U.S. Work Authorization: Yes
Job Level: New Grad/Entry Level Willing to Travel: Yes, More Than 75%
Highest Degree Attained: Masters Willing to Relocate: Yes


Objective:
Seeking a technical position in the field of VLSI Engineering and helping to achieve organizational goals.


Experience:
• Experience to Work on Verilog Modelsim and VCS tool for Logic implementation and debug and verification. Also with Synopsis tool for Synthesis. (since August 2008)

• Experience with F K Electronics working on PCB design and testing as test and co-Engineer. (June 2007 to November 2007)

• Experience to work with Cadence tool for schematic and layout designing on Static, Dynamic and mixed signal as well as high speed designs. (Jan 2008 to current)

• Hands on experience Verilog, SystemVerilog and Verilog-A on VCS as well as Modelsim tools and also the Synopsis synthesis tool. (August 2008 to current)

• Worked on the Digital as well as analog and high speed VLSI circuits Designs with Verilog for logic implementation and cadence tool for schematic and layout work. (Jan 2008 to current)

• Cheapest and most small area PLL at present time With less area, high frequency, less power and less cost of 12 to 15GHz in 45nm Technology.(Mix signal). This project is based on the unused pattern in which I removed the LPF and Charge pump with DAC and Incrementer/ Decrementer and not used any Capacitor in whole circuit. (August 2009 to current)

• 8-bit Processor with assembler design with different functionality with verilog on VCS and Modelsim tool.(August 2009 to December 2009)

• 6-Bit Digital to analog converter with thermometer code, Binary weighted in 130nm tech. (August 2009 to December 2009)

• Analog designing of 2 stage-amplifiers, current mirror and current reference circuit, Sample and hold circuit and Comparator circuit with 90nm technology with cadence tool and observed and rectify its response. (January 2009 to May 2009)

• Designed and implemented circuit simulation for Mux based Program counter, performed and verified the layout of it with 45nm technology in cadence tool, also checked its functionality with its analog-extracted view in cadence with simulation with the high speed Domino logic implementation. (January 2009 to May 2009)

• SystemVerilog and verification of the ATM switching SOC with assertion and functional coverage based verification using the VCS as well as Modelsim tool. Implement logic as well as verify with different terminology of system verilog such as assertion, covering and also used the interface implementation for common buses. (August 2009 to December 2009)

• Implemented circuit simulation for a Confuzer to unconfuzer circuit with the concept of the Networking Cryptography and test with test-bench in verilog with CRC using VCS by verilog coding and also get the synthesis circuit of schematic on synopsis tool. (August 2008 to December 2008)

• Designed and implemented circuit simulation for a 8, 16, 32, 64 bit full-adder with carry-look-ahead and ripple carry algorithm and took several analysis to get the best one on VCS by Verilog coding also synthesis with Synopsys tool in two different libraries, such as Toshiba and Class. (January 2009 to May 2009)

• Designed and implemented the Static CMOS based circuit and simulation for 8-bit ALU with 10 different functions in it, and performed and verified the layout of the full adder using mentor graphics VLSI CAD tools in Unix with 0.6um Process technology. (January 2008 to May 2008)

• SOLAR PANEL TRACKING TOWARDS SUN – FINAL YEAR PROJECT –During BE (Microcontroller based). Well appreciated in whole Gujarat University and completely new idea during 2007. (December 2006 to November 2007)

• San Jose State University, Department of physics as Grader: Assisted professor to grade homework and exam. (February 2008 to May 2008)


Education:
SAN JOSE STATE UNIVERSITY, San Jose, CA (GPA: 3.4)
Master of Science, Electrical Engineering (VLSI)

Gujarat University (PIET), Gujarat, India. (GPA: 3.9)
Bachelor of Engineering in Electronics & Communication


Affiliations:
RELATED COURSEWORK
• Semiconductor-Physical Designing, CMOS Static Design and Analysis.

• Logic Analysis and Synthesis with verilog, System Verilog - System on chip, ASIC and Digital Designing.

• VLSI Design with cadence, Semiconductor and MOSFET Devices, CMOS Circuits and digital designing, Analog Circuit Analysis, Analog and mixed signal designing, High speed Dynamic CMOS Designing.


Skills:
• Operating Systems: Windows XP, Mac,

• Languages: 1) Verilog and Verilog-A for logic implementation.
2) SystemVerilog for Logic Verification and structure implementation of SOC.
3) Language used during BE - C, Assembly Language, VHDL, JAVA.

• Software: 1) VCS and Modelsim for Verilog, SystemVerilog for Design, debug and Verification.
2) Synopsys tool for synthesis the verilog codes.
3) Cadence tool for Schematic and Layout implementation with IBM, TSMC.


Additional Information:
Respected Sir,

I am Dodia Sagar. I am a student of San Jose State University. I had just completed with my 4th semester with very good courses and at present I am doing my masters project. I am going to graduate in this May 2010 and I already applied for the OPT from which I can work as full time employee for your company. My current GPA is 3.45 and my under graduate GPA is 3.94 out of 4. My all necessary details are in my Resume. I am very hardworking and always ready to learn the new things.
I have experience of 6 projects on cadence tool with analog, digital and mixed signal circuit designs, 4 projects on Verilog, 2 on System Verilog Verification, 1 on Embedded System and many mini-projects, too. I am very honest and helpful, that you can verify from my campus job’s performance. I am also ready to relocate.
I also have experience in F K Electronics co. as test Engineer and also as Grader in physics department of San Jose State University. I have experience to work with cadence tool for Schematic, Layout and schematic as well as analog extracted simulation with spice simulator. Hands on experience to generate the logic with Verilog, SystemVerilog and Verilog-A with VCS and Modelsim tools. Experience to working with CMOS, Dynamic Domino, CPL, Zipper and Nora, CVSL, DCVSL, Mixed Signal Circuit designs.
From now I can give my whole concentration on my job. After masters still I can continuously work for 29 months without H1 as full-time employee with my OPT.

I need one chance to work with your company and I am pretty sure that I will not disappoint you. I will prove myself with my knowledge and diligence. I am very lithe to work with your company.
I will eagerly waiting for your affirmative replay.

Thank you,
Dodia Sagar N.
(MO: 408-876-3943)
(sagardodia@gmail.com, sagar_dodia@yahoo.com)



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