Senior Verification Engineers (Ref: 100) job Santa Clara California
Senior Verification Engineers (Ref: 100) job Santa Clara California
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Senior Verification Engineers (Ref: 100) Job



Employer Name: Cerium Systems, Inc SpiderID: 8651794
Location: Santa Clara, California Date Posted: 5/15/2019
Wage: Category: Computer Hardware
Job Code:
Number Of Openings: 2

Job Description:
Senior Verification Engineers (Ref: 100): Verification of complex high speed digital logic with focus on system level operation and performance. Responsible for module, chip and system verification of highly complex digital systems. Primary responsibilities will include: verification planning, testbench development, test case development, test case debug, coverage analysis, and metric/status reporting. Testbench development will include defining the architecture and implementation of: directed random test generators, coverage models, reference models and bus functional models. Test case development will include the use of directed random test generators, device driver and system applications. Draw conclusions from code, functional and assertion coverage. Development of coverage-driven, pseudo-random module and chip level test strategies, test plans, and test cases using module level and system level techniques. Write documentation, including validation report, and verification hand-off. Define experiments to identify root cause of problems. May include verification of SOC ASICs in an FPGA environment and final silicon verification/characterization. Responsible for all test software required to verify a SOC ASIC. May include integrating new designs into FPGA Tools used: VERILOG-UVM Methodology, VERILOG-OVM Methodology, Synopsys VCS, System Verilog, Cadence NCSim. Please send resumes referencing the aforementioned job title and reference number to Cerium Systems, Inc., 4701 Patrick Henry Drive, Building 6, Santa Clara, CA 95054.


Job Requirements:
Minimum Education: Masterís degree in Electronics. Minimum experience: Two (2) years. Two (2) years of experience must include two (2) years of experience in: VERILOG-UVM Methodology, VERILOG-OVM Methodology, Synopsys VCS, System Verilog, Cadence NCSim. Job Site: Santa Clara, CA. Job may involve working at various unanticipated locations throughout the United States. Travel required to the extent of relocating to various unanticipated locations throughout the United States.


Job Criteria:
Start Date:
Position Type: Full-Time Permanent
Years of Experience Required: 2
Education Required: Masters
Overnight Travel:
Vacation Time:


Contact Information:
Contact Name: Seshadri Polisetty Company Type: Employer
Company: Cerium Systems, Inc
City: Santa Clara
State: California
Zip: 95054
Web Site: http://cerium-systems.com/

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